The present invention relates to a semiconductor memory device, and more particularly to a flash memory. The flash memory can rewrite information by electric erasing and writing. Memory cells can be formed by a transistor. All memory cells or memory cell blocks can be electrically erased in a group. In the flash memory, the time for rewriting data can be shortened by the group erasing function.
FIGS. 13 to 16 show the sectional structure of the flash memory in each operating state, wherein a field effect transistor having a two-layer gate structure, which is formed on a P type silicon substrate SUB, is shown as the flash memory. The field effect transistor has a floating gate FG, a control gate CG, a source S and a drain D.
Information is written to the memory cell by injecting hot electrons generated in the vicinity of the drain into the floating gate FG to increase the threshold as shown in FIG. 13. In this case, the control gate CG has a potential of 6 V, the drain D has a potential of 5 V, and the source S and the substrate SUB have a potential of 0 V. The memory cell is erased by drawing charges from the floating gate FG to the source S to decrease the threshold by a FN (Fowler Nordhein) tunnel current as shown in FIG. 14. In this case, the control gate CG and the substrate SUB have a ground potential of 0 V, the drain D is open and the source S has a potential of 12 V. When the erasing operation has been applied for a long time, the memory cell is brought into the overerase state. Even though the potential of the control gate CG is set to 0 V, the memory cell transistor keeps the ON state.
A reversal operation to be described below can eliminate the overerase state. As shown in FIG. 15, the reversal of the memory cell is performed by injecting the hot electrons generated in the vicinity of the drain into the floating gate FG to increase the threshold in the same manner as writing. In this case, the control gate CG has a potential of 0 V, the drain D has a potential of 5 V, and the source S and the substrate SUB have a potential of 0 V.
First of all, the memory cell is in the overerase state. Consequently, a current flows in the ON state even though the control gate CG has a potential of 0 V. When the hot electrons generated in the vicinity of the drain D are injected into the floating gate FG, the threshold gradually approaches 0 V from a negative voltage. When the threshold reaches about 0 V, the current stops flowing to the memory cell and the hot electrons are not generated. For this reason, the threshold does not exceed 0 V. Thus, the overerase state is eliminated.
The memory cell is read out by setting the control gate CG to 5 V, the source S and the substrate SUB to a ground potential 0 V, and the drain D to 1 V as shown in FIG. 16. It is decided whether data is 0 or 1 depending on the current flow from the drain to the memory cell. When negative charges are accumulated in the floating gate FG, the current does not flow to the memory cell. In this case, the data is set to 0. When the negative charges are not accumulated in the floating gate FG, the current flows to the memory cell. In this case, the data is set to 1.
In the prior art, the reversal of the memory cell is carried out to eliminate the overerase state. In the read state, it is possible to increase a difference between the ON current which flows to the memory cell in the erase state and the offleak current which flows to the memory cell in the write state.
FIG. 17 shows the threshold of a memory cell transistor based on the above-mentioned operation. FIG. 18 shows the relationship between the time for the reversal operation and the offleak current of the memory cell. As is apparent from FIG. 18, the offleak current of the memory cell is decreased when the time for the reversal operation is increased, and is saturated at a certain value.
FIG. 19 shows the structure of a circuit of a memory cell array block BLKn. FIG. 20 shows the circuit structure of a memory device having four memory cell array blocks arranged thereon. FIG. 21 shows the control signal timing of the reversal operation of the whole circuit shown in FIG. 20.
The memory device according to the prior art comprises four memory cell array blocks BLK0 to BLK3. The reversal operation is sequentially performed for each block. A circuit shown in FIG. 19 will be described briefly. WL0 to WL255 designate word lines. BL0 to BL63 designate bit lines. CG0 to CG63 designate column selection gates. DL designates a data line. RVG00 designates a full group reversal control gate. SC00 designates a source control gate. SOU00 designates a common source node. VSS designates a ground voltage. SA designates a sense amplifier circuit. DVS00 designates a reversal voltage supply circuit. Qn designates an N channel MOS transistor. Qm designates a memory cell transistor.
The drains of memory cells on the different word lines are connected to a bit line. The sources of memory cells on the same word line are connected to the comon source node SOU00. The common source node SOU00 is connected to the ground voltage VSS through the N channel MNOS transistor Qn having the source control gate SC00. Each bit line is connected to the reversal voltage supply circuit DVS00 through the N channel MOS transistor Qn having the common full group reversal control gate RVG00.
Each bit line is connected to the data line DL through the N channel MOS transistor Qn having column selection gates CG0 to CG63. The data line DL is connected to the sense amplifier circuit SA. The reversal operation is performed by setting the full group reversal control gate RVG00 to a logical voltage "H" to supply a reversal voltage from the reversal voltage supply circuit DVS00 to the bit lines BL0 to BL63.
As shown in FIG. 21, the full group reversal control gates RVG00 to RVG30 are sequentially set to the logical voltage "H" so that the reversal operation is performed for the memory cell array blocks BLKO to BLK3 shown in FIG. 20. The reversal operation may be simultaneously performed for the whole device by setting the full group reversal control gates RVG00 to RVG30 to the logical voltage "H" at the same time.
The inventors have found that the following problems arise if all the flash memory cells or all the memory cell array blocks are reversed in a group. Specifically, a lot of current flows from the drains of all the memory cells to the sources thereof at once. Consequently, a voltage drop is caused by the resistance components that form the node of the source so that the potential of the source is raised. An increase in the potential of the source reduces the difference in voltage between the drain and source of the memory cell. Consequently, the current flows with difficulty as compared with the case where the potential of the source is not raised. If the current flows with difficulty, hot electrons are not often generated so that the reversal operation is not performed efficiently. In other words, the time for the reversal operation to control the offleak current of the memory cell is increased or the offleak current of the memory cell cannot fully be controlled.